ASIC Verification Engineer - Digital  (Sunnyvale, CA)

As a member of VLSI engineering design team, engineer will be responsible for implementing test plans to verify unit, subsystem, and chip level functionality in a complex SOC environment. Successful applicant will have verification experience and a solid understanding of Verilog based RTL design. This work involves working closely with design engineers to create constrained random based test-bench and test cases, to ensure adequate feature and code coverage, and to help resolve test failures. Applicant has the opportunity to help create reusable verification environments to be used across multiple projects.

Required Education and Experience:

  •  Minimum 5-7 years experience
  •  BS in EE, Computer Engineering, or equivalent field
  •  ASIC Verification focus
  •  +2 years experience with Specman or System Verilog Constrained Random test-bench knowledge
  •  +1 year experience with Assertion-Based Verification (SVA, PSL, OVL)
  •  Experience in embedded firmware (C/C++), low level drivers / silicon bring-up
  •  RTL Design Understanding (Verilog preferred)
  •  Good communication skills
  •  Detail oriented and driven

    Strongly Desired Education and Experience:

  •  MS in EE, Computer Engineering, or equivalent field
  •  Knowledge of digital video processing
  •  Emulation / silicon validation experience

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