Primary function:
Perform physical design, timing closure, and tape out functions for DTV related chip designs
Key Responsibilities:
Serve as a senior technical contributor and a technical lead in broad areas of physical design which includes floor plan, place&route, clock tree synthesis, timing closure, design for manufacturability, and tape out. Participate in physical design methodology and flow development. Also help in related areas such as package/pad planning, IR analysis, and ECO implementations.
Required Education and Experience:
BSEE or MSEE in Electrical or Computer Engineering with 10 years of experiences. Candidate should have strong background in physical design, timing closure, and advanced semiconductor process and DFM issues. Candidate should also have extensive experiences in deep submicron place&route tools and be capable of developing physical design flow and methodologies. Programming skills in perl, tcl, and C are strongly favored. Knowledge in Verilog RTL and gate-level netlist structures are also preferred.